This document is available at URL: http://csci.viu.ca/~liuh/355/OutlineCSCI355.html

Contact information

• Lecturer: Huizhu Liu
• Office: Building 315 (Physics Building), Room 211
• Email: Huizhu.Liu@VIU.CA
• Course web site: http://csci.viu.ca/~liuh/355/
• Office Hours:
• 10:00 - 12:00, Tuesdays and Thursdays
• By appointment

Timetable

• Lectures:
  
  • 10:00 - 11:30, Mondays and Wednesdays, 210/240
• Labs:
  Section F23N01: 14:30 - 16:30, Tuesdays, 315/115
  Section F23N02: 16:30 - 18:30, Tuesdays, 315/115
  

(Optional) Textbooks

Logic and Computer Design Fundamentals by M. Morris Mano and Charles R. Kime

Fundamentals of Digital Logic and Microcontrollers by M. Rafiquzzaman

Recommended Lab Texts:

Verilog for Digital Design by Frank Vahid and Roman Lysecky

Assessment: (Note that all the work MUST be done by yourself independently)

• Up to 8 Labs/Assignments -- 32%
• In-Class Midterm -- 20%
• Lab final quiz -- 8%
• Final Exam -- 40%

You MUST achieve a passing mark in weighted exam marks in order to pass the course.

Topics

• Number Systems and Codes
  • Decimal, Binary, Octal and Hexadecimal
  • Integer Encoding: 1's complement, 2's complement
  • Floating Point Number Encoding
  • Codes: ASCII, Gray Code
  • Error Detection/Correction Codes
• Boolean Algebra
  • Boolean Properties
  • Boolean equivalency
  • Canonical Forms
  • Logic Simplification
  • Karnaugh Maps
• Hardware Description Language (HDL) - Verilog
  • Nets, Variables, Number Representation
  • Structural Specification
  • Behavioral Specification (Continuous/Procedural Assignment)
  • Test Bench Construction, Synthesis
  • Vectored Signals, Generic Specification o Generate Capability
  • Arithmetic Assignment Statements
  • Operator, Task, Function
• Combinational logic and circuits
  • Ripple Carry Adders
  • Carry Lookahead Adders
  • Decoders
  • Encoders
  • Comparators
  • Multiplexers (Shannon Expansion Theorem)
  • Simple Multiplication
• Combinational Circuit Analysis and Design
• Sequential logic and circuits
  • Latches (SR, JK, D, T)
  • Flip Flops (Gated SR, D, JK, T)
  • Registers
  • Shift Registers
  • Counters
• Synchronous Sequential Circuit Analysis and Design (Finite State Machine)
• Miscellaneous Topics
  • Assembly Level Machine Organization
  • CPU, Memory, etc.

Learning Outcomes:

Upon completing this course, students should be able to:

• master the standard number and code systems;
• analyze and design combinational circuits per specification;
• analyze and design some typical sequential circuits per specification;
• simulate and test designed combinational and sequential circuits using Verilog
• enumerate typical challenges and common solution ideas in microcomputer system design.

Labs/Tutorials:

You must be enrolled in, and you must fully participate in, the (almost) weekly lab sessions.

Appeals of Grades:

Any exercise or examination grade may be appealed. However, the appeal must be made to the instructor, in writing and attached to the work in question, and within 7 days of the grade being made available to the class. The instructor reserves the right to re-grade the entire piece of work submitted on appeal, not necessarily just the component that the student believes is in error.

Grade Conversion:

The following scale will be used:

University Policy and Procedures

All students taking this course are subject to the Vancouver Island University Policy and Procedures:

The official policies of Vancouver Island University can be viewed at http://www.viu.ca/policies/.

To quickly view some policies and procedures concerning student academic code of conduct and academic misconduct, etc, view the following documents:

• Academic Integrity
• Academic Integrity (procedure)

Academic Integrity Statement

It is expected that students will know and abide by the VIU's policy on Student Academic Code of Conduct (Policy 96.01)

Standards of Academic Integrity Include, but are not limited to:

• independently producing work submitted under their own name;
  • all graded work needs to be written independently, unless expressly instructed to collaborate.
• properly and appropriately referencing all work;
• identifying all collaborators in work;
• completing examinations without giving or receiving assistance, excepting those students requiring assistance due to a documented accessibility issue;
  • the use of tutorial services, including online sites, to solve graded work is strictly prohibited.
  • the use of online sites and apps for solving mathematical problems on graded work is strictly prohibited.
• respecting the integrity of examination materials and/or the examination process; and respecting the integrity of computer security systems, software copyrights and file privacy of others.

Any academic misconduct will be dealt with in accordance with policies in effect at VIU (96.01) and may result in a final grade of "F", a report to the Dean and a permanent record in the student’s academic file. Multiple records may result in suspension from the University.

https://learningmatters.viu.ca/ready-set-go/academic-integrity
https://www.viu.ca/registration/general-regulations "Student Academic Code of Conduct"
https://isapp.viu.ca/VIUWEB/main.asp Policy - 96.01