Weekly labs and lab assignments will be posted here once they are available.

• December 5: Lab Quiz: (more) Sequential Circuit Design and Realization
  Deliverable due date: noon, 12 December 2023
  
  
• November 28: Lab 9: Sequential Circuit Design and Realization
  Deliverable due date: noon, 5 December 2023
  
  
• November 21: Lab 8: Sequential Circuit Analysis and Realization
  Deliverable due date: noon, 28 November 2023
  
  
• November 7: Lab 7: Memory Element
  Deliverable due date: noon, 14 November 2023
  
  
• October 31: No new lab tasks.
  
  
• October 24: Lab 6: Combinational Logic Application
  Deliverable due date: noon, 31 October 2023
  
  
• October 17: No new lab tasks. Prepare for the midterm (on October 18th).
  
  
• October 10: Lab 5: Circuit Analysis, re-design and realization
  Deliverable due date: noon, 17 October 2023
  
  
• October 3: Lab 4: BCD (8-4-2-1) code validator
  Deliverable due date: noon, 10 October 2023
  
  
• September 26: Lab 3: implement even parity bit generator and checker with circuits and verilog codes.
  Deliverable due date: noon, 3 October 2023
  
  
• September 19: Lab 2: implement AND and OR gate using NAND gates only with circuits and verilog codes.
  Deliverable due date: noon, 26 September 2023
  
  
• September 12: Lab 1: Introduction
  and some example Verilog files: A simulation and its test bench simulation