Next: Introduction
Automated Behavioral Testing of VHDL Components
Peter Walsh
Department of Computing Science, Malaspina University-College
900 Fifth Street, Nanaimo, B.C., V9R 5S5 Canada
Daniel Hoffman
Department of Computer Science, University of Victoria,
P.O. Box 3055, Victoria, B.C., V8W 3P6 Canada
Abstract:
Design reuse is essential for dealing with complex integrated circuits
and printed circuit boards.
The use of a hardware description language such as VHDL
is becoming a requirement for this kind of reuse.
The current practice is to model the design component in VHDL
and to test the design's behavior using a testbench,
which applyies test cases and reports
deviations of actual behavior from expected behavior.
In this paper we present VHDLGEN, a prototype method and tool
for algorithmic testing of VHDL designs,
adapted from a successful approach to testing software components.
Testing with VHDLGEN involves a special interface to the component
under test, a scripting language, and a driver generator.
VHDLGEN is oriented towards highly automated testing,
where the driver generates the inputs, runs the tests,
and checks the outputs for correctness.
We present evidence that the VHDLGEN approach is feasible.
Our experience with algorithmic testing of software components
suggests that VHDLGEN will scale up to more complex
designs and will be adaptable to designs in object-oriented HDLs
as they become available.
Peter Walsh
Sun Apr 7 09:56:15 PDT 1996