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VHDLGEN

VHDLGEN is a CAD tool that can be used to automatically generate a driver for a VHDL testbench. In contrast to software modules, VHDL components can be active. Components may interact within a testbench outside the control of the driver. As alluded to earlier, this can cause controllability and observability problems.

We address this problem by accessing the CUT through a testing interface. The testing interface makes the CUT reactive. That is, the CUT only responds to stimuli from the driver.

To illustrate the use of VHDLGEN, consider the design of simple Logical And ( LAnd) gate. Let LAnd have two binary inputs, A and B, and one binary output C. In terms of behaviour, C = A.B and, the value of C is valid 10ns after a change in value to either A or B. The entity declaration for LAnd is:

entity LAnd;
   port (A,B: in bit; C: out bit);
end LAnd;

The testing interface consists of the following VHDL procedures and functions:

procedure LAInit is
begin
   -- empty
end;

procedure LASetInputs(x,y: in bit) is
begin
   A <= x;
   B <= y;
   wait for Td; -- time delay
end;

function LAGetOutput return bit is
   variable x: bit;
begin
   out_capture(x); -- capture value
                   -- of signal C 
   return (x);
end;

LAInit is an initialization procedure and it is included to facilitate design for testability. The other subprograms allow us to set inputs and capture outputs.

The syntax of a test-case in VHDLGEN is tcase(trace, actval, expval). A trace is any sequence of calls to the CUT through the testing interface. The actval is an expression that is evaluated after the trace. It's value is taken as the ``actual value'' of the trace. expval is the value that actval is expected to have. Four test cases are necessary to exhaustively test the behaviour of LAnd. They are:

tcase(LAInit;               -- trace
      LASetInputs('0','0'), 
      LAGetOutput,          -- actual value
      '0')                  -- expected value
tcase(LAInit;
      LASetInputs('0','1'), 
      LAGetOutput, 
      '0')
tcase(LAInit;
      LASetInputs('1','0'), 
      LAGetOutput, 
      '0')
tcase(LAInit;
      LASetInputs('1','1'), 
      LAGetOutput, 
      '1')
In general, a test case takes the form tcase(, actval, expval). VHDLGEN generates VHDL code to

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Peter Walsh
Sun Apr 7 09:56:15 PDT 1996