We have described several approaches to testing VHDL designs. While interactive testing and keystroke capture/playback are widely used, algorithmic testing has significant advantages when many test cases must be run many times. As VHDL designs increase in complexity, the advantages of algorithmic testing will increase as well.
We have presented VHDLGEN, a prototype method and tool for algorithmic testing of VHDL design, adapted from a successful approach to testing software components. Testing with VHDLGEN involves a special interface to the component under test, a scripting language, and a driver generator. VHDLGEN is oriented towards highly automated testing with tests that are inexpensive to develop, execute, and maintain.
We have presented evidence that the VHDLGEN approach is feasible. Our experience with algorithmic testing of software components suggests that VHDLGEN will scale up to more complex designs and will be adaptable to test designs in object-oriented HDLs as they become available.