Make Revisited

The make tool is so important for (Unix) software developers that some additional coverage is desirable.

Basic make

The input to make is a file named either Makefile or makefile in the current directory. (We prefer the capitalized version because a directory listing in alphabetic order will show this file before all the source files which usually have names beginning with lower-case letters.)
A simple Makefile consists of a series of groups. Each group names a target (a file to be created), gives a list of prerequisites (files needed as input to create the target), and provides a build action: one or more Unix commands that will create the target file from the prerequisite files.

For example:
```
	module.o: module.c module.h useful.h
		cc -c -g module.c
	
```
specifies that module.o can be created if the files named module.c, module.h, & useful.h all exist. The command(s) to create module.o appear below.

The make algorithm

Suppose that a group is of the form:

	T: p0 p1 ... pN
		B
	where
		T is a target
		p0, p1, ..., pN are prequisites
		B is a build action

Suppose that "X < Y" means: either file X does not exist or file X's modification time precedes file Y's modification time. Intuitively, "X < Y" means "X is out of date".

Make executes the following recursive algorithm:

	boolean make(group G)
		buildFlag = false
		foreach p in {p0, p1, ..., pN}
			if there is a target for p
				if make(p)
					buildFlag = true
			else if there is a file p
				if T < p
					buildFlag = true
			else
				Error: cannot make p
		if buildFlag or file T does not exist
			execute B
			return true
		else
			return false

Makefiles need to be flexible. E.g., it would be nice to change the C compiler options from

A macro takes the form:
```
	NAME = DEFINITION 
```
For example, we can put the following definition near the top of the Makefile:
```
	CFLAGS = -g 
```
and rewrite our target/prerequisite groups like this:
```
	module.o: module.c module.h useful.h
		cc -c $(CFLAGS) module.c 
```
The definition of any make macro can be overridden on the Unix command line. Instead of editing the Makefile to change the definition of CFLAGS, we can invoke make like this, for example:
```
	make CFLAGS=-O 
```
Macro definitions are also useful for listing names of files. It is common to see Makefiles like the following:
```
	CFILES = main.c module.c useful.c useless.c input.c output.c

	HFILES = module.h useful.h useless.h input.h output.h

	SRCFILES = $(CFILES) $(HFILES)

	OBJFILES = main.o module.o useful.o useless.o input.o output.o

	TARGET = bigProg

	CFLAGS = -g

	$(TARGET): $(OBJFILES)
		cc -o $(TARGET) $(CFLAGS) $(OBJFILES)

	printAll: $(SRCFILES)
		lpr -Pmyprinter $(SRCFILES)

	module.o: module.c module.h useful.h
		cc -c $(CFLAGS) module.c

	## remainder of Makefile omitted
	
```
Note that macros have been used for both targets and prerequisites where appropriate. Further note the target printAll in the above example. When the command
```
	make printAll 
```
is executed, make will look for a file named printAll and it will presumably not find one. It therefore executes the Unix command listed below the target name. The command causes all the source code files to be printed. It does not create a file named printAll. This is OK. If we subsequently type
```
	make printAll 
```
again, we will produce another source code listing. I.e., we have tricked make into performing a useful task without actually making anything.

More Advanced Features -- make Rules

Some target/prerequisite patterns occur so frequently that they are pre-programmed into make. For example, make knows how to create a `.o' file from a `.c' file.

Thus, we can abbreviate the module.o example above to just the single line:
```
	module.o: module.h useful.h 
```
I.e., we do not have to say that module.c is needed as a prerequisite for module.o. If make is asked to build module.o (either directly or indirectly), it will check to see if there are any files named module.c, module.f, module.p ... in the current directory. If it finds a file named module.c, it will automatically execute the command:
```
	$(CC) $(CFLAGS) $(CPPFLAGS) -c module.c 
```
where CC is a macro that is defined, by default, to be cc, and CFLAGS and CPPFLAGS are defined to be empty strings.

If make were to find a file named module.f, it would invoke the Fortran77 compiler with the command:
```
	$(FC) $(FFLAGS) $(CPPFLAGS) -c module.f 
```
and so on.
To achieve flexibility, the rules for converting a `.c' file into a `.o' file, or a `.f' file into a `.o' file, etc., are not programmed into make. The rules are read from an initialization file.

The rule for converting a `.c' file into a `.o' file is specified like this:
```
	.c.o:
		$(CC) $(CFLAGS) $(CPPFLAGS) -c $< 
```
This says that if make needs to create a file with the `.o' suffix from a file with the `.c' suffix then it should run the command(s) listed below.

The notation $< refers to the name of the input file for the rule (e.g. module.c).

$< is an example of a special macro whose value depends on which make rule is currently being invoked. A list of the more useful special macros is:

`$<`	the full name of the input file to the dependency rule.
`$*`	same as `$<` but with the suffix removed.
`$@`	the full name of the current target.
`$?`	a list of prerequisites for the rule that are newer than the target.

You can create your own default rules in two steps. First, you must declare any new suffixes to make, and then you must give your new default rule.

For example, suppose that we want to have make know how to convert LaTeX files into dvi files. (LaTeX is a text formatter, a dvi file is a device-independent output file that can be viewed on a workstation or can be converted to PostScript for printing.)

The following lines in the Makefile would now suffice:
```
	.SUFFIXES: .tex .dvi
		
	.tex.dvi:
		latex $< 
```
The first line tells make that it now has to handle files with ``.tex'' and ``.dvi'' suffixes in addition to all the suffixes that it already handles.

The remaining lines provide the default rule itself.

Subsequently, the user can type a command like:
```
	make mydoc.dvi 
```
If no explicit rule specifying mydoc.dvi appears in the Makefile, and if a file named mydoc.tex exists in the current directory, make will apply our default rule and execute:
```
	latex mydoc.tex 
```

Other Features of make

The Unix commands that make issues are executed under the control of the Bourne shell (the sh program). If the Unix command needs to perform file re-direction, or use other non-trivial shell features, the command must be written in the sh command language.

If you prefer to use the C-shell, csh, you can add a line:
```
	SHELL = /bin/csh 
```
near the beginning of the Makefile.
If a Unix command issued by make should fail (signalled by returning a non-zero status code), make immediately quits. Thus, for example, if a C compilation generates error messages, make will terminate.

Occasionally, it is desirable to continue after receiving a non-zero status code. (And there are a few Unix commands which do not set an appropriate status code.) To ignore a command's status code and continue, you may prefix the command with a hyphen. E.g.
```
	module.o: module.c module.h useful.h
		-cc -c $(CFLAGS) module.c
	
```
Make, by defaults, echoes all commands that it executes to the standard output. To suppress echoing, prefix the command with an at symbol (@). E.g.
```
	module.o: module.c module.h useful.h
		@cc -c $(CFLAGS) module.c
	
```
Suppose that you have a large project consisting of many C source code files, and that you have a Makefile to compile all the files and create the executable program.

Suppose that you have built the program, e.g. you have executed:
```
	make 
```
Now suppose that you decide to fix up the comments in file foo.h. The next time you run make, all the files that depend on foo.h will be re-compiled unnecessarily. (The comment changes should not affect the program at all.)

If you run:
```
	make -t 
```
then make will reset all the timestamps on the files so that everything will appear to be up-to-date (and nothing needs to be recompiled). Make accomplishes this task by executing commands like:
```
	touch subr.o 
```
The touch command updates the named file by replacing the first byte in the file with itself. I.e., the file's contents do not change, but the modification time does.
If your Makefile causes actions to happen that you do not understand, you can try running make with the ``-d'' flag. E.g.,
```
	make -d myprog 
```
causes debugging information to be output.
The command
```
	make -n 
```
will display all the actions that make would perform in creating its target without actually performing those actions. The ``-n'' flag is useful for debugging Makefiles.
Make has been extended by the Free Software Foundation and different Unix vendors to provide support for features such as RCS, SCCS, object libraries, and conditional execution of commands. Such features will not be covered here -- refer to the on-line information.