CSCI 355 Home Page

• CAD Tools
  • Cew for C++
  • HC11 download procedure (from 261)
  • Espresso
  • Espresso Example Usage 1
  • Espresso Example Usage 2
  • Digital Logic Design
  • Verilog Tutorial

• Manuals
  • XSA-50 Manual (Xess)
  • ise 6 Quick-Start Tutorial

  • Labs 2019
    • Lab Basic Acceptence Tests
    • Intro (Last modified:Sep 22 2016 14:25
    • Lab2 (Last modified:23/09/13 20:05
    • Lab3 (Last modified:09/10/13 17:17
    • Lab4 (Last modified:30/10/13 16.23
    • Lab5 (Last modified:05/11/14 11.23
    • Lab6 (Last modified:06/11/13 10.50
    • Lab7 (Last modified:13/11/13 10.05
    • Lab8 (Last modified:13/11/13 16.05
    • Labs9 (Last modified:15/11/13 15.30
    • Lab10 (Last modified:18/09/28 08.25
    • Lab11 (Last modified:17/11/17 10.43

    • Lab0 BB photo
    • Another Lab0 BB photo
    • Pin-Out Sheet Template

  • Labs 2020
    • Dave's Tec Notes
      
    • xcircuit
    • xournal
    • Xournal on MS Windows
      
    • How to set up your .forward
      

    • Lecture 1 Slides
      
    • Lecture 2 Slides
      
    • Lecture 3 Slides
      
    • Lecture 4 Slides
      
    • Lecture 4 Readme
      
    • Lecture 5 Slides
      
    • Lecture 6 Slides
      
    • Lecture 7 Slides
      
    • Lecture 7 Readme
      
    • Lecture 8 Slides
      
    • Lecture 9 Slides
      
    • Lecture 9 Readme
      
    • Lecture 10 Slides
      
    • Lecture 11 Slides
      
    • Lecture 12 Slides
      
    • Lecture 13 Slides
      
    • Lecture 14 Slides
      
    • Lecture 16 Slides
      
    • Lecture 17 Slides
      
    • Lecture 17 (SR = 11)
      
    • Lecture 18 Slides
      
    • Lecture 19 Slides
      
    • Lecture 20 Slides
      
    • Lecture 21 Slides
      
    • Lecture 22 Slides
      

    • Lab Manual Intro (Last modified:Sep 15 2020 21:14)
    • Lab 1 Statement (Last modified:Sep 18 2020 20:31)
    • Labs 2-4 Statements (Last modified:Sep 21 2020 20:31)
    • Labs 7-8 Statements (Last modified:Sep 21 2020 20:31)

      How to submit Labs 1-4 using git
      How to submit Labs 7-8 using git
      

    • Lab 1 Readme (Last modified:Sep 22 2020 15:22)
    • Lab 2 Readme (Last modified:Sep 29 2020 14:11)
    • Lab 3 Readme (Last modified:Oct 08 2020 09:00)
    • Lab 4 Readme (Last modified:Dec 3 2020 18:00)

    • Lab 7 Readme (Last modified:Dec 3 2020 18:00)
    • Lab 8 Readme (Last modified:Dec 3 2020 18:00)

      How to submit TEST1 using git
      How to submit TEST2 using git
      

• HDL
  • Verilog Scheduling Semantics (from Std 1364-2001)
  • Nonblocking Assignments in Verilog Synthesis; Coding Styles That Kill! (Cummings)
  • Advanced Verilog Techniques Workshop (Cummings)
  • Verilog Nonblocking Assignments With Delays, Myths and Mysteries (Cummings)
  • Icarus Verilog

• Hamming Code
• VLSI Programmable Logic Devices
• FPGA and CPLD Architectures: A Tutorial
• Writing VHDL for RTL Synthesis
• Active VHDL from Aldec
• Active VHDL Application Notes (select How-To Guide)

• Green Mountain Local Docs (plus tutorial)

• ASSP Support Page for VHDL

• Past Midterm Exams
  • Midterm Exam 02
  • Midterm Exam 17

• Past Final Exams
  • Final Exam Dec 07
  • Final Exam 2015