Using data objects

This section describes how different objects can be referenced within a design. The following grammar rule for name includes all the different ways of referencing different kinds of objects. The prefix rule allows the methods to be combined in one reference. This will be seen later. The attribute name is described in the next chapter. Simple names are the names give to objects in VHDL (i.e. entities, variables, etc.). Simple names are restricted to names that begin with a letter and can be followed by any sequence of letters, numbers or the underscore character. Additionally, in VHDL'93, extended identifiers may be used. These are any sequence of characters inclosed by the backslash character. For example, declares a signal with an extended identifier. The remaining rules are described in the following sections.

Selected names
Indexed names
Slice names