Block statements

Often in digital design, a problem is logically decomposed into smaller blocks. In GM VHDL a design can be logically decomposed using the block statement. The block statement is primarily used to group a logical block of concurrent statements together for human readability and understandability. The block statement may also rename signals for internal use and looks much like the use of a component. The syntax of the statement is:

The generic and port clause declare local signals that can be used within the block statement. The generic and port maps associate actual signals to the local port and generic names. The optional expression that can follow the BLOCK keyword is called a guard expression. The guard expression can be used to "guard" signals. The section on concurrent signal assignments discusses the guarded signal assignment. A guarded signal assignment may only appear within a block and the guard expression used is the guard expression of the immediately enclosing block statement. The guard expression together with a guarded statement can be used to build a latch. For example, implements a latch, since the waveform input_data will only be assigned to latch_data, when the guard is true. In this case, the guard is the rising edge of the clock signal clk. The clk'event is an attribute reference and is true if an event has occurred on the signal clk during the current simulation cycle. Attributes are described in the next chapter.