Chapter 4 - Behavioral Descriptions

There are three different paradigms for describing digital components with VHDL, structural, data flow, and behavioral descriptions. This chapter dicusses the behavioral approach.

Section 1 - The Process Statement

The behavioral approach to modeling hardware components is different from the other two methods in that it does not necessarily in any way reflect how the design is implemented. It is basically the black box approach to modeling. It accurately models what happens on the inputs and outputs of the black box, but what is inside the box (how it works) is irrelevant. The behavioral description is usually used in two ways in VHDL. First, it can be used to model complex components that would be tedious to model using the other methods. This might be the case for example, if you wish to simulate the operation of your custom design connected to a commercial part like a microprocessor. In this case, the microprocessor is complex and its internal operation is irrelevant (only the external behavior is important) so it would probably be modeled using the behavioral style. Second, the behavioral capabilities of VHDL can be more powerful and is more convenient for some designs. In this case the behavioral description will likely imply some structure of the implementation.

Behavioral descriptions are supported with the process statement. The process statement can appear in the body of an architecture declaration just as the signal assignment statement does. The contents of the process statement can include sequential statements like those found in software programming languages. These statements are used to compute the outputs of the process from its inputs. Sequential statements are often more powerful, but sometimes have no direct correspondence to a hardware implementation. The process statement can also contain signal assignments in order to specify the outputs of the process.

Our first example of the process statement is trivial and would not normally be done in a process statement. However, it allows us to examine the process statement without learning any sequential statements first.

compute_xor: process (b,c)
begin
  a<=b xor c;
end process;

The first part

compute_xor:

is used to name the process. This part is optional. Next is the keyword process that starts the definition of a process. Following that is a list of signals in parenthesis, called the sensitivity list. Since the process statement's contents may not indicated any structural characteristics, there is no way to know when the process should be re-evaluated to update the outputs. The signal sensitivity list is used to specify which signals should cause the process to be re-evaluated. Whenever any event occurs on one of the signals in the sensitivity list, the process is re-evaluate. A process is evaluated by performing each statement that it contains. These statements (the body of the process) appear between the begin and end keywords.

This example process contains one statement, the signal assignment. Unlike signal assignments that appear outside the process statement, this signal assignment is only evaluated when events occur on the signals in the process' sensitivity list, regardless of which signals appear on the right side of the <= operators. This means it is critical to make sure the proper signals are in the sensitivity list. The statements in the body of the process are performed (or executed) in order from first to last. When the last statement has been executed the process is finished and is said to be suspended. When an event occurs on a signal in the sensitivity list, the process is said to be resumed and the statements will be executed from top to bottom again. Each process is executed once during the beginning of a simulation to determine the initial values of its outputs.

The previous section is Data Flow Descriptions - Signal Assignments.
The next section is Behavioral Descriptions - Using Variables.

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