The following is an example of a conditional signal assignment statement.
... signal d,in,en: bit; ... d<=in when en='1' else d; ...This signal assignment could be used to model a transparent latch. The right hand side of this statement is re-evaluated whenever there is an event on in,en, or d because each of these signals appear on the right side of the <= operator. The result of the expression depends on the value of en. If en is '1' then in is the value of the expression, otherwise d will be the result of the expression.
In general the conditional signal assignment can have a number of expression when condition parts, such as
target<=expression_1 when condition_1 else
expression_2 when condition_2 else
...
expression_N when condition_N else
expression_N+1;
In order to evaluate the expression on the right side, the conditions are
evaluated
from first to last until one of them evaluates to TRUE or there are none
left to evaluate. If all the conditions are false then the result of the
right hand side is the value of expression_N+1. Otherwise the
result of the right hand side is the value of expression_j,
if condition_j was the first
condition found that evaluates to TRUE.The following is an example of a selected signal assignment statement.
signal d,in0,in1,in2,in3: bit_vector (7 downto 0);
signal sel: bit_vector (1 downto 0);
with sel select
d<=in0 when "00",
in1 when "01",
in2 when "10",
in3 when "11";
This signal assignment could be used to model the operation of a multiplexer.
As with the other signal assignment statements, the right side of the
statement is re-evaluated whenever there is an event on any signal that
appears on the right side of the <= operator. Additionally, if an event occurs
on any signals appearing in the expression following the key word
with, then the
right side will be re-evaluated. To evaluate the right side, the value
of the sel signal is compared to each value from first to last of the
values following the key words when. The result of the expression is
the value of the
expression preceeding the first value found that matches the value of sel.
In other words, the result is in0 if sel="00", in1
if sel="01", in2 if sel="10" and in3 if
sel="11".In general the selected signal assignment can have an number of expression when choice parts, such as
with select_expression select target<=expression_1 when choice_1, expression_2 when choice_2, ... expression_N when choice_N;In order to evaluate the right side expression, the select_expression is first evaluated and then compared to each of the choices from first to last. If choice_j is the first value that is equal to the value of the select_expression then expression_j will be the result of the right side. It is considered an error, if the select expression does not match any of the choices. If this happens, the simulator will stop the simulation and report and error. However, the last choice can be the special choice others, which will match any value. For example, the following signal assignment is equivalent to the exclusive or of the two bits in the signal sel.
with sel select
e<='1' when "01"|"10",
'0' when others;
The | bar is used to combine two choices meaning or, as in match "01"
or "10".
So in this example, e will receive the value '1' if sel
is "01" or "10", and if sel is anything else (others) then it will
receive the value '0'.
The previous section is Data Flow Descriptions - Other
Operators.
The next section is Behavioral Descriptions - The Process
Statement.