Re-implement the SSBC's control unit using the counter
specified below.

module counter(LOAD, CE, SCLR, CLK, L, Q);

  input LOAD, CE, SCLR, CLK;
  input [7:0] L;
  Q [7:0] count;

...

endmodule

LOAD  CE  SCLR  L[7:0]     Operation     Priority
----------------------------------------------
1     x    x    load value load          0
0     1    x    X          count up      1 
0     0    1    X          clear         2 
0     0    0    X          no-operation  3 


Notes:

Deliverables:

      Counter implemented in verilog 
      (with test verification).                        
      Espresso input file, output file and 
      equations to drive the counter inputs.          
      Complete systen working (make runtest).